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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. features ? supports telcordia gr-1244-core stratum 3 ? supports g.823 and g.824 for 2048 kbit/s and 1544 kbit/s interfaces ? supports ansi t1.403 and etsi ets 300 011 for isdn primary rate interfaces ? simple hardware control interface ? accepts two input references and synchronizes to any combination of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz inputs ? provides a range of clock outputs: 1.544 mhz, 2.048 mhz, 16.384 mhz and either 4.096 mhz & 8.192 mhz or 32.768 mhz & 65.536 mhz ? hitless reference switching between any combination of valid input reference frequencies ? provides 5 styles of 8 khz framing pulses ? holdover frequency accuracy of 1 x 10 -8 ? lock, holdover and out of range indication ? selectable loop filter bandwidth of 1.8 hz or 922 hz ? less than 0.6 ns pp jitter on all output clocks ? external master clock source: clock oscillator or crystal applications ? synchronization and timing control for multi-trunk ds1/e1 systems such as dslams, gateways and pbxs ? clock and frame pulse source for st-bus, gci and other time division multiplex (tdm) buses february 2006 ordering information ZL30101QDC 64 pin tqfp trays zl30101qdg1 64 pin tqfp* trays, bake & drypack *pb free matte tin -40 c to +85 c zl30101 t1/e1 stratum 3 system synchronizer data sheet figure 1 - functional block diagram reference monitor mode control virtual reference ieee 1149.1a feedback tie corrector enable state machine frequency select mux tie corrector circuit mode_sel1:0 tck ref1 rst ref_sel tie_clr c1.5o c4/c65o c8/c32o c16o f4/f65o f8/f32o f16o osco osci master clock tdo ref0 tdi tms trst holdover hms lock ref_fail0 ref_fail1 dpll out_sel c2o e1 synthesizer ds1 synthesizer mux bw_sel
zl30101 data sheet 2 zarlink semiconductor inc. description the zl30101 stratum 3 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization for multi-trunk t1 and e1 transmission equipment. the zl30101 generates st-bus and other tdm clock and framing signals that are phase locked to one of two input references. it helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference sw itching operations and during short periods when a reference is unavailable. the zl30101 is intended to be the central timing and synchronization resource for network equipment that complies with telcordia, etsi, itu-t and ansi network specifications.
zl30101 data sheet table of contents 3 zarlink semiconductor inc. 1.0 change summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 reference select multiplexer (mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 reference monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 time interval error (tie) corrector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 digital phase lock loop (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 frequency synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 control and modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 loop filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 output clock and frame pulse selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 reference selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 measures of performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 jitter generation (int rinsic jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 holdover accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 pull-in range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 lock range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 phase slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10 time interval error (tie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.11 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.12 phase continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.13 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
zl30101 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections (64 pin tqfp, please see note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3 - reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - behaviour of the dis/requalify timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 - out-of-range thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 - timing diagram of hitless reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7 - timing diagram of hitless mode switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8 - dpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9 - mode switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 - reference switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11 - clock oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13 - power-up reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15 - input to output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16 - output timing referenced to f8/f32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
zl30101 data sheet 5 zarlink semiconductor inc. 1.0 change summary changes from november 2005 issue to february 2006 issue. page, section, figure and table numbers refer to this current issue. changes from july 2005 issue to november 2005 issue. pa ge, section, figure and table numbers refer to this current issue. changes from october 2004 issue to july 2005 issue. page , section, figure and table nu mbers refer to this current issue. changes from june 2004 issue to october 2004 issue. page, section, figure and table numbers refer to this issue. page item change 1 updated ordering information page item change 1 features added description for hitless reference switching. 23 section 6.1 removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. page item change 9rst pin specified clock and frame pulse outputs forced to high impedance 28 table ?dc electrical characteristi cs*? corrected schmitt trigger levels 32 table ?performance characteristics* - functional? gave more detail on lock time conditions page item change 1 text jitter changed to 0.6 ns from 0.5 ns 7 figure 2 added note specifying not e-pad 8 table ?pin description? added information about schmitt trigger feedback paths to c1.5o, c2o, c16o , and f8/f32o 11 section 3.2 added text about input pulse width restriction 16 section 3.4 added details on lock pin behaviour 20 section 4.4 added text and figure 10 explaining lock pin behaviour 21 section 5.0 added jitter definition
zl30101 data sheet 6 zarlink semiconductor inc. 26 section 6.4 corrected time-cons tant of example reset circuit 27 table ?absolute maximum ratings*? corrected package power rating 28 table ?dc electrical characterist ics*? corrected current consumption corrected input voltage characteri stics to reflect schmitt trigger corrected input leakage current to reflect internal pull-ups corrected output voltage note to reflect two pad strengths 29 table ?ac electrical characteristics* - input timing for ref0 and ref1 references (see figure 15)? added explanatory note 33 table ?performance characteristics*: output jitter generation - ansi t1.403 conformance? changed jitter numbers 33 table ?performance characteristics*: output jitter generation - itu-t g.812 conformance? changed jitter number 33 table ?performance characteristics* - unfiltered intrinsic jitter? changed jitter numbers, removed ui column page item change
zl30101 data sheet 7 zarlink semiconductor inc. 2.0 physical description 2.1 pin connections figure 2 - pin connections (64 pin tqfp, please see note 1) note 1: the zl30101 uses the tqfp shown in the package outline designated with the suffix qd, the zl30101 does not use the e-pad tqfp. zl30101 34 36 38 40 42 44 46 48 64 62 60 58 56 52 50 54 16 14 12 10 8 6 4 2 osco nc gnd out_sel c1.5o mode_sel1 v dd av dd ic nc rst nc agnd f4/f65o v dd ref1 nc ic c8/c32o nc c2o agnd av dd nc f8/f32o c4/c65o ref_sel 18 20 22 24 26 30 32 28 c16o f16o tie_clr ic ic osci av dd av dd av dd av core agnd agnd agnd nc nc ic ic mode_sel0 nc bw_sel ref0 v core lock hms trst gnd tdo tms holdover ic tck tdi v core av core gnd ref_fail0 ref_fail1
zl30101 data sheet 8 zarlink semiconductor inc. 2.2 pin description pin description pin # name description 1gnd ground. 0 v. 2v core positive supply voltage. +1.8 v dc nominal. 3lock lock indicator (output). this output goes to a logic high when the pll is frequency locked to the selected input reference. 4 holdover holdover (output). this output goes to a logic high whenever the pll goes into holdover mode. 5 ref_fail0 reference 0 failure indicator (output). a logic high at this pin indicates that the ref0 reference frequency has exceeded the out-of-ra nge limit or that it is exhibiting abrupt phase or frequency changes. 6ic internal bonding connection. leave unconnected. 7 ref_fail1 reference 1 failure indicator (output). a logic high at this pin indicates that the ref1 reference frequency has exceeded the out-of-ra nge limit or that it is exhibiting abrupt phase or frequency changes. 8tdo test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 9tms test mode select (input). jtag signal that controls t he state transitions of the tap controller. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 10 trst test reset (input). asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up to ensure that the device is in the normal functional stat e. this pin is internally pulled up to v dd . if this pin is not used then it should be connected to gnd. 11 tck test clock (input): provides the clock to the jtag test logi c. if this pin is not used then it should be pulled down to gnd. 12 v core positive supply voltage. +1.8 v dc nominal. 13 gnd ground. 0 v. 14 av core positive analog supply voltage. +1.8 v dc nominal. 15 tdi test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 16 hms hitless mode switching (input). the hms circuit controls phase accumulation during the transition from holdover or freerun mode to normal mode on the same reference. a logic low at this pin will cause the zl30101 to maintain the delay stored in the tie corrector circuit when it tran sitions from holdover or fr eerun mode to normal mode. a logic high on this pin will cause the zl30101 to measure a new delay for its tie corrector circuit thereby minimizi ng the output phase movement when it transitions from holdover or freerun mode to normal mode. 17 mode_sel0 mode select 0 (input). this input combined with mode_sel1 determines the mode (normal, holdover or freerun) of operation, see table 3 on page 18. 18 mode_sel1 mode select 1 (input). see mode_sel0 pin description.
zl30101 data sheet 9 zarlink semiconductor inc. 19 rst reset (input). a logic low at this input resets the device. on power up, the rst pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. when the rst pi n goes high, the device will transition into a reset state for 3 ms. in the reset state all clock and frame pulse outputs will be forced into high impedance. 20 osco oscillator master clock (output). for crystal operation, a 20 mhz crystal is connected from this pin to osci. this output is not suitable for driving other devices. for clock oscillator operation, this pi n must be left unconnected. 21 osci oscillator master clock (input). for crystal operation, a 20 mhz crystal is connected from this pin to osco. for clock oscillator operation, this pin must be connected to a clock source. 22 ic internal connection. leave unconnected. 23 gnd ground. 0 v. 24 nc no internal bonding connection. leave unconnected. 25 v dd positive supply voltage. +3.3 v dc nominal. 26 out_sel output selection (input). this input selects the signals on the combined output clock and frame pulse pins, see table 2 on page 18. 27 ic internal connection. connect this pin to ground. 28 ic internal connection. connect this pin to ground. 29 av dd positive analog supply voltage. +3.3 v dc nominal. 30 nc no internal bonding connection. leave unconnected. 31 nc no internal bonding connection. leave unconnected. 32 c1.5o clock 1.544 mhz (output). this output is used in ds1 applications. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 33 agnd analog ground. 0 v 34 agnd analog ground. 0 v 35 av core positive analog supply voltage. +1.8 v dc nominal. 36 av dd positive analog supply voltage. +3.3 v dc nominal. 37 av dd positive analog supply voltage. +3.3 v dc nominal. 38 nc no internal bonding connection. leave unconnected. 39 nc no internal bonding connection. leave unconnected. 40 agnd analog ground. 0 v 41 agnd analog ground. 0 v 42 c4 /c65o clock 4.096 mhz or 65.536 mhz (output). this output is used for st-bus operation at 2.048 mbps, 4.096 mbps or 65.536 mhz (st-bus 65.536 mbps). the output frequency is selected via the out_sel pin. pin description (continued) pin # name description
zl30101 data sheet 10 zarlink semiconductor inc. 43 c8/c32o clock 8.192 mhz or 32.768 mhz (output). this output is used for st-bus and gci operation at 8.192 mbps or for operation with a 32.768 mhz clock. the output frequency is selected via the out_sel pin. 44 av dd positive analog supply voltage. +3.3 v dc nominal. 45 av dd positive analog supply voltage. +3.3 v dc nominal. 46 c2o clock 2.048 mhz (output). this output is used for standard e1 interface timing and for st-bus operation at 2.048 mbps. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 47 c16o clock 16.384 mhz (output). this output is used for st-bus operation with a 16.384 mhz clock. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 48 f8/f32o frame pulse (output). this is an 8 khz 122 ns active high framing pulse (out_sel=0) or it is an 8 khz 31 ns active high framing pulse (out_sel=1), which marks the beginning of a frame. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 49 f4 /f65o frame pulse st-bus 2.048 mbps or st -bus at 65.536 mhz clock (output). this output is an 8 khz 244 ns active low fram ing pulse (out_sel=0), which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048 mbps and 4.096 mbps. or this output is an 8 khz 15 ns active low framing pulse (out_sel=1), typically used for st-bus operation with a clock rate of 65.536 mhz. 50 f16o frame pulse st-bus 8.192 mbps (output). this is an 8 khz 61 ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mbps. 51 agnd analog ground. 0 v 52 ic internal connection. connect this pin to ground. 53 ref_sel reference select (input) . this input selects the input reference that is used for synchronization, see table 4 on page 20. this pin is internally pulled down to gnd. 54 nc no internal bonding connection. leave unconnected. 55 ref0 reference (input). this is one of two (ref0, ref1) input reference sources used for synchronization. one of five possible frequencies may be used: 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. this pin is internally pulled down to gnd. 56 nc no internal bonding connection. leave unconnected. 57 ref1 reference (input). see ref0 pin description. 58 nc no internal bonding connection. leave unconnected. pin description (continued) pin # name description
zl30101 data sheet 11 zarlink semiconductor inc. 3.0 functional description the zl30101 is a ds1/e1 stratum 3 system synchronizer providing timing (clock) and synchronization (frame) signals to interface circuits for ds1 and e1 primary rate digital transmission links. fi gure 1 is a functional block diagram which is described in the following sections. 3.1 reference sele ct multiplexer (mux) the zl30101 accepts two simultaneous reference input sig nals and operates on their rising edges. one of them, the primary reference (ref0) or the secondary referenc e (ref1) signal can be selected as input to the tie corrector circuit based on the refe rence selection (ref_sel) input. 3.2 reference monitor the input references are monitored by two independent reference monitor blocks, one for each reference. the block diagram of a single reference monitor is shown in figure 3. for each reference clock, the frequency is detected and the clock is continuously monitored for thr ee independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from it s nominal frequency or excessive jitter. to ensure proper operation of the reference monitor circuit, the mini mum input pulse width restriction of 15 nsec must be observed. ? reference frequency detector (rfd) : this detector determines whether the frequency of the reference clock is 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz and provides this information to the various monitor circuits and the phase detector circuit of the dpll. ? precise frequency monitor (pfm) : this circuit determines whether the frequency of the reference clock is within the applicable accuracy range of 12 ppm, see figure 5. it will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. ? coarse frequency monitor (cfm) : this circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. ? single cycle monitor (scm) : this detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. 59 ic internal connection. connect this pin to ground. 60 ic internal connection. connect this pin to ground. 61 v dd positive supply voltage. +3.3 v dc nominal. 62 nc no internal bonding connection. leave unconnected. 63 tie_clr tie corrector circuit reset (input). a logic low at this input resets the time interval error (tie) correction circuit re sulting in a realignment of t he input phase with the output phase. 64 bw_sel filter bandwidth selection (input). this pin selects the bandwidth of the dpll loop filter, see table 1 on page 18. set continuously high to track jitter on the input reference closely or temporarily high to allow the z l30101 to quickly lock to the input reference. pin description (continued) pin # name description
zl30101 data sheet 12 zarlink semiconductor inc. figure 3 - reference monitor circuit exceeding the thresholds of any of the monitors forces the corresponding ref_fail pin to go high. the single cycle and coarse frequency failure flags force the dpll into holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for mo re than 2.5 s. the single cycle and coarse frequency failures must be absent for 10 s to let the timer requalify the input reference signal as va lid. multiple failures of less than 2.5 s each have an accumulative effect and will disqua lify the reference eventually. this is illustrated in figure 4. figure 4 - behaviour of the dis/requalify timer when the incoming signal returns to normal (ref_fail= 0), the dpll returns to normal mode with the output signal locked to the input signal. each of the monitors has a built-in hysteresis to prevent flickering of the ref_fail status pin at the threshold boundaries. the precise frequency monitor and the timer do not affect the mode (holdover/normal) of the dpll. reference frequency detector single cycle monitor precise frequency monitor coarse frequency monitor dis/requalify timer ref0 / ref1 or or ref_dis= reference disrupted. this is an internal signal. mode select state machine holdover ref_dis ref_fail0 / ref_fail1 2.5 s 10 s current ref timer ref_fail scm or cfm failure holdover
zl30101 data sheet 13 zarlink semiconductor inc. figure 5 - out-of-range thresholds the precise frequency monitor?s failure thresholds are compatible with telcordia gr-1244-core stratum 3 as shown in figure 5. it will take the precise frequency monito r up to 10 s to qualify or disqualify the input reference. 3.3 time interval error (tie) corrector circuit the tie corrector circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from holdover mode to normal mode. on recovery from holdover mode (dependent on the hms pi n) or when switching to another reference input, the tie corrector circuit measures the phase delay between the current phase (feedback si gnal) and the phase of the selected reference signal. this delay value is stored in th e tie corrector circuit. this circuit creates a new virtual reference signal that is at the same phase position as t he feedback signal. by using th e virtual reference, the pll minimizes the phase transient it experiences when it switches to another reference input or recovers from holdover mode. the delay value can be reset by applying a logic low pu lse to the tie corrector circuit clear pin (tie_clr ). a minimum reset pulse width is 20 ns. this results in a ph ase alignment between the input reference signal and the output clocks and frame pulses as shown in figure 15 on page 29 and figure 16 on page 31. the speed of the phase alignment correction is limited to 61 s/s when bw_sel=0. convergence is always in the direction of least phase travel. in general the tie corr ection should not be exercised when holdover mode is entered for short time periods. tie_clr can be kept low continuously. in that case the output clocks will always be aligned with the selected input reference. this is illustrated in figure 6. 0 ppm +4.6 ppm -4.6 ppm 0 7.4 12 9.2 4.6 4.6 -4.6 -13.8 -15 -10 0 -5 5 15 frequency offset [ppm] out of range out of range out of range in range in range in range c20 10 -9.2 -12 16.6 13.8 -4.6 -7.4 -16.6 c20: 20 mhz master clock on osci c20 c20 c20 clock accuracy
zl30101 data sheet 14 zarlink semiconductor inc. figure 6 - timing diagram of hitless reference switching the hitless mode switching (hms) pin enables phase hitl ess returns from freerun and holdover modes to normal mode in a single reference operation. a logic low at the hms input disables the tie corrector ci rcuit updating the delay value thereby forcing the output of the pll to gra dually move back to the origin al point before it went into holdover mode. (see figure 7). this prevents accumulati on of phase in network elements. a logic high (hms=1) enables the tie corrector circuit to update its delay value thereby preventing a large output phase movement after return to normal mode. this causes accumulation of phase in network elements. in both cases the pll?s output can be aligned with the input reference by setting tie_clr low. regardless of the hms pin state, reference switching in the zl30101 is always hitless unless tie_clr is kept low continuously. locked to ref1 ref0 output clock tie_clr = 1 tie_clr = 0 ref1 ref0 output clock ref1 locked to ref1 ref0 output clock ref1 ref0 output clock ref1 locked to ref0 locked to ref0
zl30101 data sheet 15 zarlink semiconductor inc. figure 7 - timing diagram of hitless mode switching examples: hms=1 : when 10 normal to holdover to normal mode transi tions occur and in each case the holdover mode was entered for 2 seconds, then the accumulated phase change (mtie) could be as large as 330 ns. - phase holdover_drift = 0.01 ppm x 2 s = 20 ns - phase mode_change = 0 ns + 13 ns = 13 ns - phase 10 changes = 10 x (20 ns + 13 ns) = 330 ns where: - 0.01 ppm is the accuracy of the holdover mode - 0 ns is the maximum phase discontinuity in the tr ansition from the normal mode to the holdover mode ref phase drift in holdover mode hms = 0 normal mode return to normal mode ref output clock ref output clock ref output clock phase drift in holdover mode normal mode return to normal mode output clock ref output clock ref output clock hms = 1 tie_clr =0 ref output clock tie_clr =0 ref output clock
zl30101 data sheet 16 zarlink semiconductor inc. - 13 ns is the maximum phase discontinuity in the transi tion from the holdover mode to the normal mode when a new tie corrector value is calculated hms=0 : when the same ten normal to holdover to normal mode changes occur and in each case holdover mode was entered for 2 seconds, then the overall mtie would be 20 ns. as the delay value for the tie corrector circuit is not updated, there is no 13 ns measurement error at this point. the phase can still drift for 20 ns when the pll is in holdover mode but when the pll enters normal mode agai n, the phase moves back to the original point so the phase is not accumulated. 3.4 digital phase lock loop (dpll) the dpll of the zl30101 consists of a phase detector, a limite r, a loop filter, a digitally controlled oscillator (dco) and a lock indicator, as shown in figure 8. the data path from the phase detector to the limiter is tapped and routed to the lock indicator that provides a lock indication which is output at the lock pin. figure 8 - dpll block diagram phase detector - the phase detector compares the virtual refer ence signal from the tie corrector circuit with the feedback signal and provides an error signal corresponding to the phase differ ence between the two. this error signal is passed to the limiter circuit. limiter - the limiter receives the error signal from the phas e detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slope of 61 s/s or 9.5 ms/s, see table 1. loop filter - the loop filter is similar to a first order low pa ss filter with a narrow or wide bandwidth suitable to provide system synchronization or line card timing, see table 1. the wide bandw idth can be used to closely track the input reference in the presence of ji tter or it can be temporarily enabled for fast locking to a new reference (1 s lock time). state select from control state machine feedback signal from frequency select mux dpll reference to frequency synthesizer virtual reference from tie corrector circuit limiter loop filter digitally controlled oscillator phase detector lock indicator lock
zl30101 data sheet 17 zarlink semiconductor inc. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchroniza tion method of the dco is dependent on the state of the zl30101. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequenc y equal to the frequency that the dco was generating in normal mode. the frequency in holdover mode is calcul ated from frequency samples stored 26 ms to 52 ms before the zl30101 entered holdover mode. in freerun mode, the dco is free running with an accu racy equal to the accuracy of the osci 20 mhz source. lock indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-window for a certain time. the selected phas e-lock-window guarantees t he stable operation of the lock pin with maximum network jitter and wander on the reference input. if the dpll is locked and then goes into holdover mode (auto or manual), the lock pin will initially stay high for 1 s. if at that point the dpll is still in holdover mode, t he lock pin will go low; subsequently the lock pin will not return high for at least the full lock-time duration. in freerun mode t he lock pin will go low immediately. 3.5 frequency synthesizers the output of the dco is used by the frequency synthesizers to generate the c1.5o, c2o, c4o , c8o, c16o, c32o and c65o clocks and the f4o , f8o, f16o , f32o and f65o frame pulses which are synchronized to the selected reference input (ref0 or ref1). the frequency synthesiz ers use digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. the clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads. 3.6 state machine as shown in figure 1, the control stat e machine controls the tie corrector ci rcuit and the dpll. the control of the zl30101 is based on the inputs mode_sel1:0, ref_sel and hms. 3.7 master clock the zl30101 can use either a clock or crystal as t he master timing source. fo r recommended master timing circuits, see the applications - master clock section.
zl30101 data sheet 18 zarlink semiconductor inc. 4.0 control and modes of operation 4.1 loop filter selection the loop filter settings can be selected through the bw_sel pin, see table 1. for the zl30101 to be compliant with telcordia gr-1244-core stratum 3, bw_sel must be set low. 4.2 output clock a nd frame pulse selection the output clock and frame pulses of the frequency synthesizers are availabl e in two groups controlled by the out_sel input. table 2 lists the supported comb inations of output cl ocks and frame pulses. 4.3 modes of operation the zl30101 has three possible manual modes of operat ion; normal, holdover and freerun. these modes are selected with the mode select pins mode_sel1 and mode_sel0 as is shown in table 3. transitioning from one mode to the other is controlled by an external controller. 4.3.1 freerun mode freerun mode is typically used when an independent clock s ource is required, or i mmediately following system power-up before network synchronization is achieved. in freerun mode, the zl30101 provides timing and sync hronization signals which are based on the master clock frequency (supplied to osci pin) only, and are not synchronized to the reference input signals. bw_sel detected ref frequency loop filter bandwidth phase slope limiting 0 any 1.8 hz 61 s/s 1 8 khz 58 hz 9.5 ms /s 1 1.544 mhz, 2.048 mhz, 8.192 mhz, 16.384 mhz 922 hz 9.5 ms /s table 1 - loop filter settings out_sel generated clocks generated frame pulses 0 c1.5o, c2o, c4o , c8o, c16o f4o , f8o, f16o 1 c1.5o, c2o, c16o, c32o, c65o f16o , f32o, f65o table 2 - clock and frame pulse selection mode_sel1 mode_sel0 mode 0 0 normal (with automatic holdover) 0 1 holdover 10 freerun 1 1 reserved (must not be used) table 3 - operating modes
zl30101 data sheet 19 zarlink semiconductor inc. the freerun accuracy of the output clock is equal to the accuracy of the master clock (osci). so if a 4.6 ppm output clock is required, th e master clock must also be 4.6 ppm. see applications - section 6.2, ?master clock?. 4.3.2 holdover mode holdover mode is typically used for short durations wh ile network synchronization is temporarily disrupted. in holdover mode, the zl30101 provides timing and synchr onization signals, which are not locked to an external reference signal, but are based on st orage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal. when in normal mode, and locked to the input refere nce signal, a numerical value corresponding to the zl30101 output reference frequency is stored al ternately in two memory locations ev ery 26 ms. when the device is switched into holdover mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.01 ppm. two factors affect the accuracy of holdover mode. one is drift on the master clock while in holdover mode, drift on the master clock directly affects the holdover mode accu racy. note that the absolute master clock (osci) accuracy does not affect holdover accuracy, only the change in osci accuracy while in holdover mode. for example, a 4.6 ppm master clock may have a temperature coefficient of 0.1 ppm per c. so a 10 c change in temperature, while the zl30101 is in holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of 1 ppm. which is much greater than the 0.01 ppm of the zl30101. the other factor affecting the accuracy is large jitter on the re ference input prior to the mode switch. 4.3.3 normal mode normal mode is typically used when a system clock sour ce, synchronized to the network is required. in normal mode, the zl30101 provides timing and frame synchroniz ation signals, which are synchronized to one of two reference inputs (ref0 or ref1). the input reference signal may have a nominal frequency of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. t he frequency of the reference inputs are automatically detected by the reference monitors. when the zl30101 comes out of reset while normal mode is selected by its mode_sel pins then it will initially go into holdover mode and generate clocks with the accuracy of its free running local oscillator (see figure 9). if the zl30101 determines that its selected re ference is disrupted (see figure 3), it will remain in holdover until the selected reference is no longer disrupted or the external c ontroller selects another refer ence that is not disrupted. if the zl30101 determines that its selected reference is not di srupted (see figure 3) then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin. if hms=0 then the zl30101 will transition directly to normal mode and it will align its output signals with its selected input reference (see figure 7). if hms=1 then the zl30101 will transition to normal mode via the tie correction state and the phase difference betw een the output signal s and the selected input re ference will be maintained. when the zl30101 is operating in normal mode, if it determ ines that its selected refe rence is disrupted (figure 3) then its state machine will cause it to automatically go to holdover mode. when the zl30101 determines that its selected reference is not disrupted then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin (see figure 9). if hm s=0 then the zl30101 will transition directly to normal mode and it will align its output signals with its input reference (see fi gure 7). if hms=1 then the zl30101 will transition to normal mode via the tie corr ection state and the phase difference between the output signals and the input refe rence will be maintained. if the reference selection changes because the value of the ref_sel1:0 pins changes, the zl30101 goes into holdover mode and returns to normal mode through the ti e correction state regardless of the logic value on hms pin. the zl30101 provides a wide bandwidth loop filter sett ing (bw_sel=1), which enables the pll to lock to an incoming reference in approximately 1 s.
zl30101 data sheet 20 zarlink semiconductor inc. figure 9 - mode switching in normal mode 4.4 refere nce selection the active reference input (ref0, ref1) is selected by t he ref_sel pin as shown in ta ble 4. if the logic value of the ref_sel pin is changed when the dpll is in normal mode, the zl30101 will perform a hitless reference switch. when the ref_sel inputs are used to force a change from t he currently selected reference to another reference, the action of the lock output will depend on the relative frequency and phase offset of the old and new references. where the new reference has enough frequency offset a nd/or tie-corrected phase of fset to force the output outside the phase-lock-window, the lock output will de-a ssert, the lock-qualify timer is reset, and lock will stay de-asserted for the full lock-time duration. where the new referenc e is close enough in frequency and tie-corrected phase for the output to stay within the phase-lock-window, the lock output will remain asserted through the referenc e-switch process. ref_sel (input pin) input reference selected 0ref0 1ref1 table 4 - reference selection ref_dis=1: current selected reference disrupted (see figure 3). this is an internal signal. ref_ch= 1: reference change, a change in the ref_sel pin. this is an internal signal. tie correction (holdover=1) holdover (holdover=1) ref_dis=0 ref_ch=1 ref_dis=0 and ref_dis=1 (ref_dis=0 and hms=1) or ref_ch=1 ref_dis=1 rst ref_ch=0 and hms=0 normal (holdover=0)
zl30101 data sheet 21 zarlink semiconductor inc. figure 10 - reference sw itching in normal mode 5.0 measures of performance the following are some pll performance indi cators and their corresponding definitions. 5.1 jitter timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. wander is defined as the low-frequency variation of the clock e dges from their ideal positions in time. high and low frequency variation imply phase oscillation frequencies re lative to some demarcation frequency. (often 10 hz or 20 hz for ds1 or e1, higher for sonet/sdh clocks.) jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 5.2 jitter generation (intrinsic jitter) generated jitter is the jitter produced by the pll and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its ou tput jitter. generated jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. generated jitter is usually measured with various bandlimiting filters depending on the applicable standards. 5.3 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencie s) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. 5.4 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the zarlink digital plls two inter nal elements determine the jitter attenuat ion; the internal low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to, for example, 61 s/s. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e ., attenuated). since intrinsic jitter is always present, jitter attenuation will appear to be lowe r for small input jitter signals than for large ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (for example 75% of the spec ified maximum tolerable input jitter). ref1 ref0 ref_sel lock lock time note: lock pin behaviour depends on phase and frequency offset of ref1.
zl30101 data sheet 22 zarlink semiconductor inc. 5.5 frequency accuracy frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 5.6 holdover accuracy holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques . for the zl30101, the stora ge value is determined while the device is in normal mode and locked to an external reference signal. 5.7 pull-in range also referred to as capture range. this is the input freq uency range over which the pll must be able to pull into synchronization. 5.8 lock range this is the input frequency range ov er which the synchronizer must be able to maintain synchronization. 5.9 phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the output signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. anot her way of specifying the phase slope is as the fractional change per time un it. for example; a phase slope of 61 s/s can also be specified as 61 ppm. 5.10 time interval error (tie) tie is the time delay between a given ti ming signal and an ideal timing signal. 5.11 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a give n timing signal and an ideal timing signal within a particular observation period. 5.12 phase continuity phase continuity is the phase difference between a given timi ng signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the pll after a signal disturbance due to a reference switch or a mode change. the observation period is usually t he time from the disturbance, to just after the synchronizer has settled to a steady state. 5.13 lock time this is the time it takes the pll to frequency lock to t he input signal. phase lock occurs when the input signal and output signal are aligned in phase with respect to each othe r within a certain phase distance (not including jitter). lock time is affected by many factors which include: ? initial input to output phase difference, ? initial input to output frequency difference, ? pll loop filter bandwidth,
zl30101 data sheet 23 zarlink semiconductor inc. ? pll phase slope limiter, ? in-lock phase distance. the presence of input jitter makes it difficult to define when the pll is locked as it may not be able to align its output to the input within the required phase distance, dependen t on the pll bandwidth and the input jitter amplitude and frequency. although a short lock time is desirable, it is not always possible to achiev e due to other synchronizer requirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performa nce (limiter) results in longer lock times. 6.0 applications this section contains zl30101 application specific details for power supply decoupling, reset operation, clock and crystal operation. 6.1 power supply decoupling jitter levels on the zl30101 output clocks may increase if the device is exposed to excessive noise on its power pins. for optimal jitter performance, the zl30101 device should be isolated from noise on power planes connected to its 3.3 v and 1.8 v supply pins. for recommended common layout practices, refer to zarlink application note zlan-178. 6.2 master clock the zl30101 can use either a clock or cr ystal as the master timing source. za rlink application note zlan-68 lists a number of applicable osc illators and crystal s that can be used with the zl30101. 6.2.1 clock oscillator when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, phase noise, output rise and fall times, output levels and duty cycle. 1 frequency 20 mhz 2 tolerance 4.6 ppm 3 rise & fall time < 10 ns 4 duty cycle 40% to 60% table 5 - typical clock oscillator specification
zl30101 data sheet 24 zarlink semiconductor inc. the output clock should be connected directly (not ac co upled) to the osci input of the zl30101, and the osco output should be left open as shown in figure 11. figure 11 - clock oscillator circuit 6.2.2 crystal oscillator alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in fi gure 12. the telcordia gr1244 -core stratum 3 requirements for holdover stability and freerun accuracy may not be met with this crystal oscillator circuit. the accuracy of a crystal oscillator depends on the cryst al tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified with a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9 ppm to the frequency deviation. consequent ly, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. a typical crystal oscillator specification and circuit is shown in table 6 and figure 12 respectively. +3.3 v 20 mhz out gnd 0.1 f +3.3 v osco zl30101 osci no connection
zl30101 data sheet 25 zarlink semiconductor inc. figure 12 - crystal oscillator circuit 6.3 power up sequence the zl30101 requires that the 3.3 v rail is not powered-up later than the 1.8 v ra il. this is to prevent the risk of latch-up due to the presence of parasitic diodes in the io pads. two options are given: 1. power up the 3.3 v rail fully first, then power up the 1.8 v rail 2. power up the 3.3 v rail and 1.8 v rail simultaneously, en suring that the 3.3 v rail voltage is never lower than the 1.8 v rail voltage minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate) 1 frequency 20 mhz 2 tolerance as required 3 oscillation mode fundamental 4 resonance mode parallel 5 load capacitance as required 6 maximum series resistance 50 ? table 6 - typical crystal oscillator specification osco 1 m ? 20 mhz zl30101 osci 100 ? 1 h the 100 ? resistor and the 1 h inductor may improve stability and ar e optional.
zl30101 data sheet 26 zarlink semiconductor inc. 6.4 reset circuit a simple power up reset circuit with about a 60 s reset low time is shown in figure 13. resistor r p is for protection only and limits current into the rst pin during power down conditions. the re set low time is not critical but should be greater than 300 ns. figure 13 - power-up reset circuit +3.3 v rst r p 1 k ? c 10 nf r 10 k ? zl30101
zl30101 data sheet 27 zarlink semiconductor inc. 7.0 characteristics 7.1 ac and dc electr ical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated. * voltages are with respect to ground (gnd) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd_r -0.5 4.6 v 2 core supply voltage v core_r -0.5 2.5 v 3 voltage on any digital pin v pin -0.5 6 v 4 voltage on osci and osco pin v osc -0.3 v dd + 0.3 v 5 current on any pin i pin 30 ma 6 storage temperature t st -55 125 c 7 tqfp 64 pin package power dissipation p pd 500 mw 8 esd rating v esd 2kv recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 2.97 3.30 3.63 v 2 core supply voltage v core 1.62 1.80 1.98 v 3 operating temperature t a -40 25 85 c
zl30101 data sheet 28 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. figure 14 - timing parameter measurement voltage levels dc electrical ch aracteristics* characteristics sym. min. max. units notes 1 supply current with: osci = 0 v i dds 3.0 6.5 ma outputs loaded with 30 pf 2 osci = clock, out_sel=0 i dd 32 52 ma 3 osci = clock, out_sel=1 i dd 42 71 ma 4 core supply current with: osci = 0 v i cores 022 a 5osci = clocki core 14 20 ma 6 schmitt trigger low to high threshold point v t+ 1.43 1.85 v all device inputs are schmitt trigger type. 7 schmitt trigger high to low threshold point v t- 0.80 1.10 v 8 input leakage current i il -105 105 av i = v dd or 0 v 9 high-level output voltage v oh 2.4 v i oh = 8 ma for clock and frame-pulse outputs, 4 ma for status outputs 10 low-level output voltage v ol 0.4 v i ol = 8 ma for clock and frame-pulse outputs, 4 ma for status outputs ac electrical charact eristics* - timing parameter measur ement voltage levels (see figure 14) characteristics sym. cmos units notes 1 threshold voltage v t 1.5 v 2 rise and fall threshold voltage high v hm 2.0 v 3 rise and fall threshold voltage low v lm 0.8 v t ir, t or timing reference points all signals v hm v t v lm t if, t of
zl30101 data sheet 29 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * period min/max values are the limits to avoid a single-cycle fault detection. short-term and long-term average periods must b e within out-of-range limits. * supply voltage and operating temperature are as per recommended operating conditions. figure 15 - input to output timing ac electrical charact eristics* - input timing for ref0 and ref1 references (see figure 15) characteristics symbol min. typ. max. units 1 8 khz reference period t ref8kp 121 125 128 s 2 1.544 mhz reference period t ref1.5p 338 648 950 ns 3 2.048 mhz reference period t ref2p 263 488 712 ns 4 8.192 mhz reference period t ref8p 63 122 175 ns 5 16.384 mhz reference period t ref16p 38 61 75 ns 6 reference pulse width high or low t refw 15 ns ac electrical character istics* - input to output timing for ref0 and ref1 references (see figure 15) characteristics symbol min. max. units 1 8 khz reference input to f8/f32o delay t ref8kd 0.7 2.0 ns 2 1.544 mhz reference input to c1.5o delay t ref1.5d 2.4 3.0 ns 3 1.544 mhz reference input to f8/f32o delay t ref1.5_f8d 2.5 3.3 ns 4 2.048 mhz reference input to c2o delay t ref2d 2.0 3.0 ns 5 2.048 mhz reference input to f8/f32o delay t ref2_f8d 2.2 3.3 ns 6 8.192 mhz reference input to c8o delay t ref8d 5.2 6.2 ns 7 8.192 mhz reference input to f8/f32o delay t ref8_f8d 5.5 6.3 ns 8 16.384 mhz reference input to c16o delay t ref16d 2.6 3.3 ns 9 16.384 mhz reference input to f8/f32o delay t ref16_f8d -28.0 -27.2 ns ref0/1 t refp t ref8kd , t ref_f8d t refw t refd t refw f8_32o output clock with the same frequency as ref
zl30101 data sheet 30 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical char acteristics* - output timing (see figure 16) characteristics sym. min. max. units notes 1 c1.5o pulse width low t c1.5l 323.1 323.7 ns outputs loaded with 30 pf 2 c1.5o delay t c1.5d -0.6 0.6 ns 3 c2o pulse width low t c2l 243.2 243.8 ns 4 c2o delay t c2d -0.4 0.3 ns 5f4o pulse width low t f4l 243.5 244.2 ns 6f4o delay t f4d 121.5 122.2 ns 7c4o pulse width low t c4l 121.2 122.3 ns 8c4o delay t c4d -0.3 1.0 ns 9 f8o pulse width high t f8h 121.6 123.2 ns 10 c8o pulse width low t c8l 60.3 61.2 ns 11 c8o delay t c8d -0.4 0.2 ns 12 f16o pulse with low t f16l 60.6 61.1 ns 13 f16o delay t f16d 29.9 30.8 ns 14 c16o pulse width low t c16l 28.7 30.8 ns 15 c16o delay t c16d -0.5 1.4 ns 16 f32o pulse width high t f32h 30.0 31.8 ns 17 c32o pulse width low t c32l 14.8 15.3 ns 18 c32o delay t c32d -0.5 0.1 ns 19 f65o pulse with low t f65l 14.8 15.4 ns 20 f65o delay t f65d 7.1 8.0 ns 21 c65o pulse width low t c65l 7.2 8.1 ns 22 c65o delay t c65d -1.0 0.0 ns 23 output clock and frame pulse rise time t or 1.0 2.0 ns 24 output clock and frame pulse fall time t of 1.2 2.3 ns
zl30101 data sheet 31 zarlink semiconductor inc. figure 16 - output timing referenced to f8/f32o t f8h t f4d f4o c16o f8o t f16l f16o c8o c4o c2o t f16d t f4l t c16d t c8d t c4d t c1.5d t c16l t c8l t c4l t c2l t c1.5l t f32h c65o f32o t f65l f65o c32o t f65d t c65d t c32d t c65l t c32l f32o, c32o, f65o and c65o are drawn on a larger scale than the other waveforms in this diagram. t c2d c1.5o
zl30101 data sheet 32 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. 7.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. ac electrical char acteristics* - osci 20 mhz master clock input characteristics sym. min. max. units notes 1 oscillator tolerance -4.6 4.6 ppm 2 duty cycle 40 60 % 3 rise time 10 ns 4 fall time 10 ns performance characteristics* - functional characteristics min. max. units notes 1 holdover accuracy 0.01 ppm 2 holdover stability 0 ppm deter mined by stability of the 20 mhz master clock oscillator 3 freerun accuracy 0 ppm determined by accuracy of the 20 mhz master clock oscillator 4 capture range -12 +12 ppm the 20 mhz master clock oscillator set at 0 ppm 5 reference out of range threshold (including hysteresis) -9.2 -12 +9.2 +12 ppm the 20 mhz master clock oscillator set at 0 ppm lock time 7 1.8 hz loop filter 40 s 12 ppm frequency offset, hms=1, tie_clr =1, bw_sel=0 8 58 hz and 922 hz loop filter 1 s 12 ppm frequency offset, hms=1, tie_clr =1, bw_sel=1 output phase continuity (mtie) 9 reference switching 13 ns 10 switching from normal mode to holdover mode 0ns 11 switching from holdover mode to normal mode 13 ns output phase slope 12 1.8 hz filter 61 s/s bw_sel=0 13 58 hz and 922 hz filter 9.5 ms/s bw_sel=1
zl30101 data sheet 33 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* : output jitter generation - ansi t1.403 conformance signal ansi t1.403 jitter generation requirements zl30101 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain ds1 interface 1 c1.5o (1.544 mhz) 8 khz to 40 khz 0.07 ui pp 45.3 0.30 ns pp 2 10 hz to 40 khz 0.5 ui pp 324 0.32 ns pp performance characteristics* : output jitter generation - itu-t g.812 conformance signal itu-t g. 8 1 2 jitter generation requirements zl30101 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain e1 interface 1 c2o (2.048 mhz) 20 hz to 100 khz 0.05 ui pp 24.4 0.36 ns pp performance characteristics* - unfiltered intrinsic jitter characteristics max. [ns pp ] notes 1 c1.5o (1.544 mhz) 0.45 2 c2o (2.048 mhz) 0.47 3 c4o (4.096 mhz) 0.42 4 c8o (8.192 mhz) 0.42 5 c16o (16.384 mhz) 0.56 6 c32o (32.768 mhz) 0.46 7 c65o (65.536 mhz) 0.49 8 f4o (8 khz) 0.40 9 f8o (8 khz) 0.33 10 f16o (8 khz) 0.43 11 f32o (8 khz) 0.36 12 f65o (8 khz) 0.42
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